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| Preliminary Information T73LVP22 Dual 3.3V LVTTL/LVCMOS-to-Differential LVPECL Translator Applications * Multiple LVPECL clock sources General Description The TLSI T73LVP22 is a general-purpose dual LVTTL (LVCMOS)-to-differential LVPECL translator operating from a single +3.3V supply. The device has two independent channels that accept an LVTTL or LVCMOS input and provide differential LVPECL outputs referenced to the positive supply rail. The small 8pin SOIC package makes it ideal for applications which require the translation of multiple clocks or data signals, and where cost, performance and size are of critical importance. The T73LVP22 is 100K PECL compatible and is a pin-for-pin replacement for the MC100EPT22D. Features * * * * * 350pS typical propagation delay Operating Frequency > 1 GHz Differential LVPECL outputs Flow-through pinout Q, Q1 outputs default low with input (D) open * * * ESD rating >2000V (Human Body Model) or >200V (Machine Model) -40 oC to +85 oC operating temperature range Available in standard 8-pin SOIC package Figure 1. Functional Block Diagrams & Pin Assignments (Top View) 8-pin SOIC Q 1 LVPECL LVTTL/ LVCMOS 8 VDD Qn 2 7 D Q1 3 LVPECL LVTTL/ LVCMOS 6 D1 Q1n 4 5 GND See page 4 for package outline drawing and ordering information. T73LVP22PI Page 1 Rev A February 23, 2004 TLSI Incorporated, 770 Park Avenue, Huntington NY 11743 * (631) 755-7005 * Fax 631-755-7626 * www.tlsi.com T73LVP22 Table 1. Pin Description Name Q, Q1 Qn, Q1n VDD D, D1 GND Legend: Preliminary Information Description LVPECL data outputs LVPECL complementary data outputs Connect to +3.3V LVCMOS/LVTTL data inputs Connect to ground I = Input O = Output P = Power supply connection Type O O P I P Pin # 1, 3 2, 4 8 7, 6 5 Table 2. Absolute Maximum Ratings (each channel) Symbol VDD VIN IOUT TSTG Parameter Supply voltage Input voltage Output current Storage temperature Conditions Referenced to GND Referenced to GND Continuous -65 -0.5 Min Typ Max +5.0 VDD 50 +150 Units V V mA o C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and correct functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 3. Operating Conditions (each channel) Symbol VDD TA VIH VIL Parameter Power Supply Voltage Ambient Temperature Input HIGH Voltage Input LOW Voltage Conditions Min +3.0 -40 +2.0 +0.8 Typ +3.3 Max +3.6 +85 Units V o C V V T73LVP22PI Page 2 Rev A February 23, 2004 TLSI Incorporated, 770 Park Avenue, Huntington NY 11743 * (631) 755-7005 * Fax 631-755-7626 * www.tlsi.com T73LVP22 Preliminary Information Table 4. DC Characteristics (each channel) TA = -40oC to +85oC, VDD = +3.0V to +3.6V unless otherwise stated below. Symbol IIH IIL VIK VOH Parameter Input HIGH Current Input LOW Current Input Clamp Diode Voltage Output HIGH Voltage (1, 2) o Conditions VIN =+2.7V VIN = +0.5V IIN = -18mA -40 C +25 C +85oC (1, 2) o o Min Typ Max 100 1 -1.2 Units A A V mV mV mV mV mV mV mA VDD = +3.3V 2220 2220 2220 2320 2320 2320 1520 1520 1520 46 2420 2420 2420 1620 1620 1620 VOL Output LOW Voltage -40 C +25 C +85oC o VDD = +3.3V 1420 1420 1420 IDD Notes: Power Supply Current Total both channels, no load 1. The T73LVP22 is designed to meet these specifications after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board. 2. Q, Q1 and Qn, Q1n outputs are loaded with 50 ohms to VDD-2 volts. Table 5. AC Characteristics (each channel) TA = -40oC to +85oC, VDD = +3.0V to +3.6V Symbol tPLH tPHL tr/tf fMAX fMAX Parameter Propagation Delay Propagation Delay (1) (1) Conditions To Output Differential To Output Differential 20%-80%, Q/Qn LVTTL or LVCMOS input 750mV peak-to-peak sine wave centered around 1.5V Min Typ 350 350 Max 500 500 200 Units ps ps ps GHz GHz Output Rise/Fall time Maximum Input Frequency Maximum Input Frequency (2) 80 130 >1 >1 Notes: 1. Q, Q1 and Qn, Q1n outputs are loaded with 50 ohms to VDD-2 volts. 2. Measured using a 750mV peak-to-peak, 50% duty cycle clock source. T73LVP22PI Page 3 Rev A February 23, 2004 TLSI Incorporated, 770 Park Avenue, Huntington NY 11743 * (631) 755-7005 * Fax 631-755-7626 * www.tlsi.com T73LVP22 Preliminary Information Figure 2. Package Outline (8-pin SOIC) Table 6. Ordering Information No. of Pins 8 8 Part Number T73LVP22-S08 T73LVP22-S08-TNR Marking T73LVP22 T73LVP22 Shipping/Packaging Tubes Tape & Reel Package SOIC SOIC Temperature -40C to +85C -40C to +85C T73LVP22PI Page 4 Rev A February 23, 2004 TLSI Incorporated, 770 Park Avenue, Huntington NY 11743 * (631) 755-7005 * Fax 631-755-7626 * www.tlsi.com |
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